Proving the chip works

A modern SoC has billions of transistors and an astronomically large space of possible states. You cannot test them all, and you only get one shot: an undiscovered bug that reaches silicon can cost a respin worth millions of dollars and months of schedule. So verification engineers build elaborate testbenches that drive the design with constrained-random stimulus, model what the correct answer should be, and automatically check that the design agrees — across RTL, gate-level models and, ultimately, the physical part. Industry studies have for years put verification at the majority of total chip-development effort. It is the unglamorous discipline that decides whether a tape-out succeeds.

SyoSil: verification as a craft

SyoSil, based in Taastrup, is a consulting and engineering firm that has spent 15+ years doing exactly this — complex ASIC, FPGA and System-on-Chip verification across a wide range of application areas, using SystemVerilog/UVM, formal and property checking, verification IP and virtual prototyping. It is a pure expertise business: senior engineers who are brought in precisely because verification is hard and getting it wrong is expensive.

The SyoSil UVM Scoreboard

At the heart of any UVM testbench is the scoreboard — the component that compares what the design produced against what the reference model says it should have produced. Get the scoreboard architecture wrong and the whole testbench becomes brittle and hard to reuse. SyoSil's engineers built a better one and then gave it away.

The SyoSil UVM Scoreboard (uvm_syoscb) is released as open source under the Apache licence and maintained publicly on GitHub. Its key idea is architectural separation: the reference model and the scoreboard are completely decoupled, a clean split that most UVM scoreboards do not make. That separation of concerns lets the same scoreboard simultaneously interface and compare any number of models — design models (RTL, gate level), timed or untimed reference models written in SystemVerilog, SystemC or Python, and even physical devices (FPGA or ASIC) — via TLM connections or a simple function-based API. The result is a scoreboard that scales from a small block-level testbench to chip-level and silicon bring-up without being rewritten.

SyoSil presented the methodology at DVCon US in 2015 ("Versatile UVM Scoreboarding", Andersen, Jensen & Steffensen) and has maintained it as a community resource ever since. For a firm of its size to contribute a reusable building block to the worldwide UVM ecosystem — the de-facto standard methodology for chip verification — is a quiet but real piece of Danish influence on how chips get verified everywhere.

A broader Danish verification bench

SyoSil is the clearest example, but verification expertise runs through the wider Danish design-services and IP community — teams that verify their own silicon-proven IP, and consultancies that provide verification, FPGA prototyping and production-test firepower on demand. It is the natural partner discipline to the country's turnkey and design-services stronghold.